In chiplet integration applications, various chips from different vendors can be integrated into one package structure using the Universal Chiplet Interconnect Express (UCIe) standard. Fan-Out Chip on Substrate (FOCoS) is a promising advanced package that can achieve high channel density and high bandwidth. However, crosstalk in high-speed signals is a major factor impacting signal integrity. To effectively mitigate coupling noise between fine lines, an optimized signal-to-ground trace layout is essential. The design process outlined in this paper not only significantly reduces design cycle time but also addresses transmission loss and crosstalk effects in the die-to-die (D2D) area, thereby evaluating interconnect routing capabilities to meet UCIe x32 and x64 specifications.
In this paper, the design objectives target UCIe-A x32 and x64 for FOCoS. The proposed design process begins with confirming the arrangement structure, followed by using 2D fast simulations to identify the optimal layout design. Performance is then validated through 3D simulations. The results confirm that the 6L GSG and 8L GSG design structures proposed in this study meet the specifications for UCIe-A x32 and x64 within the FOCoS framework.
Published in: 2024 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)
