Advanced RDL Packaging
2.5D and 3D IC Packaging
ASE's 2.5D and 3D IC technologies integrate logic, memory, power, and optical components at very high interconnect density to meet growing performance, bandwidth, latency, and energy-efficiency requirements.
What is 2.5D and 3D IC packaging?
In a 2.5D structure, two or more active chips sit side by side on a silicon interposer, creating extremely dense die-to-die connections. In a 3D structure, active chips are stacked to shorten interconnects and reduce package footprint.
These architectures are increasingly important chiplet-integration platforms because they combine high packaging density with strong energy efficiency. ASE has brought pioneering 2.5D solutions, including packages with High Bandwidth Memory, into mass production.
Benefits of 2.5D and 3D IC packaging
A TSV silicon interposer bridges the fine-pitch capability gap between integrated circuits and an organic assembly substrate while supporting continued I/O scaling.
- Ultra-high routing density down to 0.4/0.4µm line and space
- More than 400 micro-bumps per square millimeter and scalable I/O pitch
- Homogeneous or heterogeneous memory, power, and optical integration
- Options for embedded decoupling capacitors or active devices
- Package reliability suitable for automotive requirements
Applications
2.5D and 3D IC packaging is used to integrate HBM with high-end GPUs, FPGAs, network switches, routers, and AI accelerators. Chiplet adoption is extending these methods into CPUs, mobile application processors, silicon photonics, and display-driver products.
- AI training and inference
- Data-center and 5G infrastructure
- High-performance graphics and FPGA systems
- Optical and mobile compute platforms