2.5D
Two or more active chips sit side by side on a silicon interposer, giving extremely high die-to-die interconnect density.
Solutions
2.5D and 3D IC Packaging
Overview
Stacking and side-by-side die integration for the bandwidth and efficiency that AI, 5G and HPC demand.
As 5G, AI and high-performance computing spread, demand keeps rising for chips with more performance, lower latency, more bandwidth and better power efficiency. 2.5D and 3D technologies deliver on all four.
ASE is an established leader in 2.5D, with pioneering solutions that helped bring advanced ASIC and HBM products to market. To keep that momentum, ASE is adding high-density Fan-Out technology for die stacking and multi-die solutions, from high-density data centers to consumer and mobile devices.
What is it
What is 2.5D & 3D IC packaging?
2.5D / 3D are packaging methodology for including multiple IC inside the same package. In recent years, 2.5D and 3D have become an ideal chiplet-integration platform thanks to their very high packaging density and energy efficiency. ASE is a pioneer here, and launched the world's first mass production of a 2.5D IC package with High Bandwidth Memory (HBM).
Comparison
3D
Active chips are stacked, for the shortest interconnects and the smallest package footprint.
Benefits
ASE's 2.5D/3D solution integrates GPU, CPU and memory alongside a decoupling capacitor.
A silicon interposer with Through-Silicon Vias (TSV) bridges the fine-pitch gap between the assembly substrate and the IC, and keeps the pad-pitch scaling path open without being limited by substrate technology.
Key advantages
- Ultra-high routing density (L/S 0.4/0.4 µm)
- Ultra-high I/O density (>400 µbumps/mm²) with I/O-pitch scalability
- Homogeneous or heterogeneous memory, power and/or optics integration
- Interposer can embed a decoupling capacitor or active devices
- Excellent reliability, meeting automotive requirements
Applications
2.5D/3D IC packaging is used mainly to integrate HBM in:
- High-end GPUs
- High-end FPGAs
- Network switches and routers for data centers and 5G infrastructure
- AI accelerators for AI training
In the chiplet era, 2.5D and 3D will play a growing role in CPUs, mobile application processors, silicon photonics, display-driver ICs and more.
