Vertically Integrated Packaging
VIPack™
VIPack™ is ASE's vertically integrated advanced packaging platform for the AI era, combining ultra-high-density interconnect, heterogeneous integration, and a collaborative co-design ecosystem from architecture through high-volume production.
Overview
System-level integration for the AI era
AI workloads require exceptional performance, memory bandwidth, and energy efficiency. As conventional scaling reaches practical limits, advanced packaging has become a strategic system-innovation tool rather than a final back-end step.
VIPack™ integrates multiple chips in a dense, high-performance system and gives AI, HPC, and data-center designs the bandwidth, power delivery, and scalability their architectures require.
ASE combines advanced RDL processes, embedded integration, 2.5D and 3D technologies, and manufacturing data so customers can move from system architecture to production with fewer design iterations.
Co-design
Integrated Design Ecosystem™
ASE's platform-level co-design ecosystem connects silicon, package, and system domains to optimize signal integrity, thermal performance, power delivery, and manufacturability.
Integrated workflows, reusable design data, and AI-assisted simulation reduce design cycles and help complex chiplet architectures reach production sooner.
Six core technology pillars
FOPoP
High-density RDL-based fan-out package-on-package for thin vertical integration.
FOCoS
Fan-out chip-on-substrate for high-I/O chiplet and HBM integration.
FOCoS-Bridge
Embedded silicon bridges provide dense, localized die-to-die connectivity.
FOSiP
Fan-out System-in-Package for compact system-level heterogeneous integration.
2.5D and 3D IC
TSV and die-stacking architectures for high-density vertical integration.
Co-Packaged Optics
Optical integration for AI infrastructure and high-I/O data systems.
Core capabilities
- Fine-pitch, high-bandwidth interconnect between disaggregated SoCs, HBM, and accelerators
- Cross-domain co-optimization for signal integrity, thermal performance, and power delivery
- Advanced networking and co-packaged optics for greater I/O bandwidth density and lower energy per bit
- Ultra-thin SiP options for edge and mobile AI with RF, analog, and passive integration
- A scalable platform aligned with future process nodes and architecture roadmaps