Solutions
Overview
Semiconductors are now a visible driver of the AI era, and AI workloads are pushing performance, bandwidth, and energy-efficiency demands beyond what conventional scaling can deliver. Innovation is increasingly determined by system-level integration rather than node shrink alone.
Advanced packaging turns multiple chips into a single high-performance system, delivering the density, efficiency, and scalability required for next-generation AI and data-center architectures. It has shifted from a back-end step to a strategic lever for system innovation.
VIPack™ is ASE’s vertically integrated advanced packaging platform for AI, HPC, and data-center applications. It combines ultra-high-density interconnect, heterogeneous integration, and a co-design ecosystem to shorten the path from architecture to production and to enable bandwidth, power delivery, and system performance targets required by AI computing.
A platform-level co-design ecosystem supports optimization across silicon, package, and system domains, reducing iteration cycles and accelerating deployment.
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Six core technology pillars
High-density RDL-based fan-out PoP.
Fan-out + substrate approach for high-density integration
Bridge-based extension for denser die-to-die connectivity
Fan-out SiP for system-level integration
TSV architectures for heterogeneous integration and vertical stacking
Optical integration for AI infrastructure and high-I/O systems
Core capabilities
Enables tight coupling of disaggregated SoCs with HBM and advanced accelerators to support massive data movement, low-latency communication, and power integrity needed for AI training and inference.
Co-design across silicon/package/system improves signal integrity, thermal performance, and power delivery while reducing design iterations and time-to-deployment.
Supports advanced networking and co-packaged optics to increase I/O bandwidth density and reduce energy per bit—key for next-generation AI clusters and data centers.
Provides ultra-thin system-in-package options that integrate RF, analog, and passive components within RDL layers to meet aggressive form-factor, thermal, and power constraints.
Aligns with evolving process nodes and architectural roadmaps, serving as a foundation for future AI, HPC, and data-centric compute platforms.
