Advanced RDL Packaging
FOCoS-Bridge
FOCoS-Bridge embeds small, fine-line silicon bridges inside a fan-out RDL to create high-bandwidth, low-latency, energy-efficient links between processors, accelerators, and memory without a full silicon interposer.
Localized silicon bridge integration
Positioned within VIPack™, FOCoS-Bridge uses small silicon pieces with routing layers as the in-package interconnect between chiplets such as a GPU and HBM. The bridges are embedded only where two dies need ultra-fine connectivity.
This architecture targets the memory-bandwidth bottleneck with interposer-like signal and power integrity while avoiding reticle-size constraints and reducing silicon area and cost.
Fabrication process
Bridge dies and copper posts are placed on a temporary carrier, molded, ground to expose interconnects, and built up with RDL. ASIC and HBM dies are then attached and molded before the carrier is removed, C4 bumps are formed, and the fan-out package is mounted to an organic substrate.
Scalable performance for AI and HPC
Submicron line-and-space bridges deliver a die-edge connection density far beyond traditional organic flip-chip packages. The structure can also embed decoupling capacitors or active dies to improve power delivery and provide direct access to memory and I/O functions.
- Multi-die and HBM integration for AI, data-center, server, and networking systems
- High I/O counts and high-speed die-to-die transmission
- Memory and passive integration for APUs, CPUs, GPUs, and chiplets
- Interposer-class electrical performance with localized silicon
