Solutions

Fan-Out Packaging

Overview

Fan-out is any package whose connections fan out past the chip surface, enabling more external I/O.

Dies are embedded in an epoxy mold (no substrate or interposer), positioned on a reconstituted wafer or panel, then given an RDL and solder balls. As a true chip-scale WLP, it avoids Fan-In WLP's die-surface I/O limit by redistributing I/O onto the over-mold.

Fan-In WLP

All RDL traces are routed in towards the center of the die

Fan-Out WLP

RDL traces are routed both inwards and outwards beyond the limits of the die

Overview

Fan-out shrinks the die footprint, integrates multiple dies, and enables true SiP.

Die shrinkage: ball placement beyond the die area
Heterogeneous & homogeneous integration with excellent connectivity
SiP: combine dies with MEMS, filters, crystals and passives in a small package

Comparative advantages

vs. flip-chip

Slightly smaller footprint
Lower profile
Better electrical performance
Better thermal performance
Substrate-less package
SiP and 3D integration advantage

vs. Fan-In WLCSP

Higher board-level reliability
Fan-out area to counter the pad limitation issue, adaptable to customer needs
The use of known good die (KGD)
Better thermal performance
Built-in back-side protection
No restriction in bump pitch
SiP and 3D integration advantage

Structures & processes

Chip-First

Chips embedded first, then the RDL. Lower-cost, low-I/O; but die shift, protrusion and warpage limit complex multi-chip/SiP use.

Chip-Last (RDL-first)

RDL pre-formed on the carrier, then chips added by flip-chip bond. Fewer KGD concerns, ultra-fine pitch (e.g. 2 µm) and better electrical performance.