System-in-Package
3D SiP
ASE's 3D System-in-Package assembles active and passive components on three or four sides of interconnected substrates, increasing functional density for wireless, wearable, IoT, edge-computing, and sensor products.
What is 3D SiP?
3D SiP uses top and bottom substrates connected by signal-routing interposers. Flip-chip CSPs, wafer-level packages, bare silicon, MEMS, crystals, oscillators, and other passives can be mounted on both sides of both boards.
Compared with a double-side SiP, the structure can reduce area by more than 13% while adding less than 10% to package thickness.
Assembly and advantages
The production flow is organized around interposer assembly, top-board assembly, and bottom-board module assembly, using SMT, molding, sawing, and shielding processes.
- Smaller form factor
- Highly integrated electronic functionality
- Short interconnects and improved electrical performance
Applications
The platform supports package sizes from approximately 6×6mm² to 30×30mm² and is suited to watches, earphones, wireless chargers, RF front-end modules, and sensor systems.
Its central advantage is the consolidation of heterogeneous chips and components into a comparatively small, modular package.