aCSP™ and WLCSP
Direct chip-scale attachment with polyimide, PBO, and thicker-copper RDL options for analog, logic, RF, power, and portable products.
Other Packaging
Wafer Level Packaging
ASE's wafer-level portfolio spans true chip-scale packages, advanced fan-out structures, and integrated passive devices, delivering thin profiles, short electrical paths, low power, and high performance from client devices through cloud infrastructure.
Packaging processed in wafer form
Wafer-level methods complete critical package structures before the wafer is singulated. This batch approach supports very small and thin products while maintaining high-density interconnect and short paths to the system board.
ASE applies WLP to portable electronics, communications, automotive radar, VR/AR, autonomous systems, robotics, networking, and high-performance cloud computing.
ASE Wafer Level Packaging offerings
Advanced WLP
A die-down fan-out package with mold compound surrounding the die, adding I/O capacity without a substrate while improving electrical and thermal performance.
Wafer Level IPD
A low-loss glass process for custom RF passives such as resonators, filters, diplexers, baluns, transformers, and inductors.
Performance and integration
- True chip-size, low-profile packages
- Fine RDL and multilayer fan-out routing
- Single- and multi-die embedded structures
- High-Q integrated passive devices on low-loss glass
- Turnkey compatibility with QFN, BGA/LGA, flip chip, and WLCSP assembly
