Other Packaging
Bumping Services
ASE forms solder and copper-pillar interconnects at wafer scale for flip chip and wafer-level packages, providing a robust electrical, mechanical, and thermal interface from advanced nodes through high-volume consumer products.
What is wafer bumping?
Bumps or balls are fabricated across the wafer before it is diced. Eutectic, lead-free, high-lead, and copper-pillar structures connect each finished die to its substrate and influence package signal, power, mechanical, and thermal behavior.
Flip chip adoption has expanded beyond high-end devices because short bump interconnects improve bandwidth and power distribution while reducing package size and weight.
ASE wafer bumping capabilities
ASE operates 200mm and 300mm bumping facilities in Kaohsiung and supports printing, plating, redistribution, backside processing, sorting, assembly, and final test as an integrated turnkey service.
Continued investment with foundries and device manufacturers has extended the platform to polyimide repassivation, RDL, and copper low-k bumping for advanced process nodes.
Copper-pillar technology
Copper pillars maintain a stable chip-to-substrate standoff and are well suited to fine-pitch interconnect below 45µm. Their mechanical stiffness and current distribution support reliable, high-performance packages without the bridging risk of larger solder bumps.
- Fine-pitch interconnect
- Strong electrical performance
- High electromigration and thermal reliability
- Consumer, computing, and communications applications
