Chip First
FOCoS-CF
ASIC chiplets face down and connect directly to a 2/2µm RDL through copper vias, without micro-bumps between the silicon and fan-out RDL.
Advanced RDL Packaging
FOCoS
ASE's Fan-Out Chip on Substrate technology creates short, high-density die-to-die connections for multi-chip packages, offering high I/O capability and strong electrical performance for AI, HPC, networking, and server products.
What is Fan-Out Chip on Substrate?
FOCoS is a fan-out package flip-chip mounted on a high-pin-count BGA substrate. Its redistribution layer builds short connections between multiple chips; the completed fan-out package is handled like a single die when mounted to the substrate.
ASE FOCoS package offerings
Chip Last
FOCoS-CL
An ASIC and two HBM stacks sit side by side and connect through 2/2µm RDL and copper micro-bumps.
Embedded Bridge
FOCoS-Bridge
A fine-line silicon bridge embedded in the fan-out RDL links an ASIC and HBM only where dense interconnect is required.
Performance, applications, and design enablement
Removing the full silicon interposer can reduce package cost while delivering lower insertion loss, tighter impedance control, and lower warpage. Existing fan-out and flip-chip methods also help accelerate time to market.
FOCoS serves packages with more than 1,000 I/Os in networking, servers, AI, and machine-learning systems. ASE's validated Assembly Design Kit supports customer planning and physical verification before and during design implementation.
- Thinner package structure
- Shorter die-to-die interconnect
- High I/O count
- Lower-cost alternative to full-interposer 2.5D
