ASE FOPoP package-on-package

Advanced RDL Packaging

FOPoP

ASE's Fan-Out Package on Package is a thin RDL-based vertical integration platform that improves electrical and thermal performance for mobile processors, optical networking, and other products where bandwidth and form factor are critical.

What is Fan-Out Package on Package?

FOPoP combines a fan-out bottom package with a standard package mounted above it. Fine-pitch copper posts connect top and bottom RDL routing planes through the mold, replacing the interposer used by a conventional PoP.

The RDL-first wafer-level process enables thinner, finer traces while keeping the top and bottom packages separable for qualification, sourcing, yield, and logistics.

FOPoP stacked package architecture
What is Fan-Out Package on Package (FOPoP)? diagram
Fabrication Process of FOPoP diagram
Fabrication Process of FOPoP diagram

Dense vertical integration

A substrate-less bottom package lowers parasitic inductance and shortens the electrical path. Double-sided RDL, landside capacitors, and near-die deep-trench capacitors can add routing and power-integrity capability for advanced silicon nodes.

  • Nearly 40% lower profile than substrate-based package-on-package structures
  • Higher interconnect density through finer RDL line and space
  • Shorter electrical paths and improved thermal performance
  • Known-good top packages can be tested before final assembly
Fabrication Process of FOPoP diagram
Fabrication Process of FOPoP diagram

Mobile and networking applications

For networking and co-packaged optics, 3D stacking shortens the path between photonic and controller ICs. ASE reports electrical-path reduction of up to 3× and bandwidth-density gains of up to 8× for optical-engine integration.

FOPoP also supports application processors with memory, ASICs with antenna-in-package modules, automotive electronics, and compact AR, VR, and MR devices where package height and battery space are at a premium.

FOPoP Applications diagram
AP + Memory (4G/5G) diagram
ASIC + Antenna (5G) diagram
FOPoP Tech Brief

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