The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant challenges arise in terms of warpage and stress, both of which pose risks to manufacturing processes and reliability testing. In this study, we employed the ANSYS Mechanical simulation software to build three-dimensional numerical models based on the FOCoS platform, encompassing both package-level and wafer-level structures. These models were used to analyze the in-process warpage and structural stress under various configurations. Simulation results indicated that wafer-level warpage increases as more fan-out layers are stacked. To mitigate this issue, we explored various factors, such as altering the carrier’s coefficient of thermal expansion (CTE), adjusting its thickness, or varying the fan-out layer thickness. Additionally, our findings revealed that the stress within the re-distribution layer (RDL) also escalates with an increasing number of fan-out layers. The findings gained from this research not only enhance our understanding of the mechanical challenges in FOCoS-CL packages but also provide valuable guidelines for the design and material selection to improve package reliability and performance.
Conclusions
The three-dimensional finite element model was successfully validated using warpage measurements obtained from Shadow Moiré and optical equipment, with an error margin of less than 10%. This validated model serves as a reliable tool for assessing wafer-level warpage and RDL stress in FOCoS-CL packages.
- The wafer-level warpage was found to increase significantly with the number of RDL layers due to the CTE mismatch between the FORDL structure and the glass carrier.
- Increasing the CTE of the glass carrier 25% can reduce warpage by approximately 13% for a 6 layers structure. Other effective strategies to reduce wafer-level warpage include increasing the thickness, CTE, and modulus of the glass carrier. –
- Changes in the number of RDL layers have minimal impact on package-level warpage, indicating that substrate and lid material selection play a more crucial role in controlling package-level deformation.
- The stress on the RDL layer, which is closest to the substrate, increases with the number of RDL layers due to the higher CTE of the substrate. The interaction between the substrate and the RDL layers becomes more significant as the number of RDL layers increases, leading to higher stress levels in the RDL.
Published in: 2024 IEEE 26th Electronics Packaging Technology Conference (EPTC) DOI: 10.1109/EPTC62800.2024.10909677
