Po Yu Liao; Ian Ho; David Lai; Yu-Po Wang; Karen Chen; Hsin-Chih Shih; Dao-Long Chen; David Tarng
The popularity of fifth-generation wireless systems will push package development toward high-performance and heterogeneous-integration forms. Electronic products will be thinner and smaller, with higher speed and I/O density, so bump diameter and bump pitch designs will become smaller or narrower to meet bump-density requirements.
Packaging creates more semiconductor assembly-process challenges, including non-wetting and bridge issues during die bonding. Bump shift and warpage mismatch across the X, Y, and Z axes can affect FCCSP assembly because of the coefficient-of-thermal-expansion mismatch between die and substrate.
To reduce these effects, we combine three-dimensional digital image correlation technology and shadow moiré technology to analyze three-dimensional displacement. Digital image correlation checks X/Y-axis displacement, while shadow moiré checks Z-axis displacement.
The method helps identify an optimum bump-layout design and uses shadow-moiré results to define high-risk die-bond areas with an interface-analysis system. Combining the methods can prevent bump shift and warpage mismatch, reduce die-bond process yield loss, and shorten the new-product-introduction development timeline.
Published in: 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
