Cloud Computing

While chiplet architecture presents numerous advantages, it also brings about complexities in design and manufacturing. In particular, connecting multicore processor dies with stacked memory dies requires point-to-point interconnections, with the number of memory dies being proportional to the number of cores on the processor die. This has led to an increased demand for advanced packaging that features a higher number of interconnects and larger body sizes.

In addition, as power densities increase, managing heat dissipation across heterogeneous components is critical to maintaining performance and reliability. Innovations in Thermal Interface Material (TIM), vapor chamber lid, liquid cooling and immersion cooling, are required to meet those challenges.

The implementation of Co-Packaged Optics (CPO) introduces significant challenges for OSATs, particularly in assembly complexity. Integrating components such as lasers, optics, fiber array units (FAUs), and silicon integrated circuits (ICs) across different wafer nodes requires meticulous attention to detail, especially in the integration of electronic integrated circuits (EICs) and photonic integrated circuits (PICs). For the integration of EIC and PIC, chip-on-wafer 3D stacking is an effective method to minimize the interconnection distance between the two, thereby significantly improving bandwidth density and energy efficiency.

Another critical issue is optical alignment and coupling, Active Alignment (AA) is often required to optimize optical coupling, but this process can hinder production efficiency. The industry is shifting towards detachable FAU solutions to improve reparability, though achieving sub-micron alignment accuracy remains a challenge. One promising approach involves utilizing wafer-level optical couplers to expand the laser beam size, thereby increasing coupling tolerance and enabling more scalable assembly.

After high voltage power delivery (e.g., ±400 V or 800V) is introduced into data center facilities, it is converted to lower voltages in multiple stages before being utilized by microprocessors. However, at higher power levels, routing losses from the last DC-DC converter on the power delivery platform to the microprocessor can become significant, negatively impacting overall system efficiency.

To mitigate this issue, the traditional lateral configuration—where power blocks or voltage regulator modules (VRMs) are positioned alongside the processor on the motherboard—is being replaced by Vertical Power Delivery (VPD). This approach positions power conversion components, such as on-board power modules, directly beneath the AI processors (xPUs), allowing power regulation to occur as close to the compute silicon as possible. Additionally, high-frequency, fully integrated voltage regulators (IVRs) must be implemented at the point of load to ensure a rapid response to transients and to achieve switching frequencies that may exceed 100 MHz. By regulating voltage right at the point of load, the system experiences reduced voltage droop during rapid compute transients, enabling AI xPUs to maintain higher clock speeds and deliver more consistent performance.

The ASE VIPack™ platform delivers a comprehensive set of advanced packaging technologies engineered to meet the performance, bandwidth, and power-density requirements of next-generation AI systems. This platform integrates high-density RDL-based Fan-Out Chip-on-Substrate (FOCoS), Fan-Out Chip-on-Substrate-Bridge (FOCoS-Bridge), and TSV-based 2.5D/3D IC architectures to support highly heterogeneous integration. VIPack™ enables fine-pitch, high-bandwidth horizontal and vertical interconnects critical for tightly coupling disaggregated SoCs with High Bandwidth Memory (HBM) and advanced accelerators. Backed by the Integrated Design Ecosystem™ (IDE), VIPack™ promotes co-design across silicon, package, and system domains, optimizing signal integrity, thermal performance, and power delivery while reducing design iteration cycles and overall time to market.

By utilizing coplanar top-surface structures, the package height can be aligned with that of various chiplets. This design allows for a cold plate to be attached directly to the chiplets, significantly reducing thermal resistance between each chiplet and the lid. Additionally, the package lids can be equipped with micro-channels to support water cooling or evaporative cooling solutions.

ASE FOCoS-Bridge allows the integration of IVR dies that integrates the power transistors and control circuits and Deep Trench Capacitor (DTC) dies in the fan-out layer to enable fine grain power management. The IVR dies are embedded in close proximity to AI chiplets to bypass the majority of the power distribution network (PDN) and associated impedance.

VIPack™ supports advanced networking and co-packaged optics (CPO) integration, enabling higher I/O bandwidth density and lower energy per bit. We have successfully demonstrated a CPO device that overcomes the integration challenge of assembling multiple optical engines with an ASIC in a large-format package. For networking, our CPO solution presents a viable alternative to current faceplate-pluggable (FPP) solutions. For compute applications, it enables the integration of CPUs, GPUs, and XPUs with optics into a single, high-speed co-packaged solution.

ASE provides advanced interconnect technologies, such as micro bumps or Cu pillar bumps, to enable the integration of the EIC on top of the PIC, forming a Photonic 3D architecture. This configuration offers superior thermal management and supports data transmission rates exceeding 200G per lane. In addition, ASE employs a high-accuracy bonding process to precisely attach optical couplers on the PIC wafer at locations aligned with tapered waveguides or grating couplers. This helps to create a detachable optical interface between FAUs and PICs, facilitating wafer-scale testing, supporting detachable FAUs, and reducing sensitivity to wavelength variations, ultimately supporting Dense Wavelength Division Multiplexing (DWDM) systems.

ASE has introduced powerSiP™, a transformative power delivery platform designed to reduce signal and transmission loss while addressing current density challenges. The powerSiP™ platform enables a vertically integrated multi-stage 3D VRM that reduces voltage droop during rapid compute transients and eliminates the need for large external decoupling networks, freeing up board space when compared to traditional side-by-side configurations.

The 3D VRM typically consists of two substrates to accommodate a variety of components, e.g., power blocks, controllers, and decoupling capacitors. ASE offers a variety of vertically interconnecting technologies, using components such as solder balls, copper blocks, substrate interposers and copper pillars. These flexible options enable the integration of various components with different heights and I/O pitches to fulfill specific design needs.